A self-refreshing DRAM is a dynamic random access memory which has an autonomous refresh circuit, and multiplexed addressing of RAS and CAS signals which corresponds to that of a dynamic random access memory. A pseudo static random access memory (SRAM) is a self-refreshing DRAM having nonmultiplexed addressing. A self-refreshing interruptable DRAM is a self-refreshing DRAM with an output pin which applies a wait signal to the microprocessor while the refresh on the DRAM is occurring.
DRAMs are composed of a plurality of memory cells in which each cell consists of a transistor network and an intrinsic capacitor. The transistors are used to charge and discharge the capacitors to certain voltage levels. The capacitors then store the voltages as binary bits, 1 or 0, representative of the voltage levels. The binary 1 is referred to as a "high" and the binary 0 is referred to as a "low." The voltage value of the information stored in the capacitor of a memory cell is called the logic state of the memory cell. Due to parasitic capacitance leakage, the memory cells must be refreshed periodically to keep the capacitors charged or discharged and to ensure the memory preservation. A refresh cycle normally involves cycling through the memory and performing a read/write operation in each location of the memory in turn during a sleep mode. The sleep mode is typically characterized as a low power mode having no active read or write operations. One common method of refreshing DRAMs is by a row refresh approach. It is necessary to refresh each row of memory in the DRAM device within a time period of 7 to 125 microseconds. In order to accomplish this there are two basic approaches which can be used. One is to stop the processor from executing the current program and refresh all rows of memory sequentially. This is classified as a burst operation. Another approach is to interrupt the microprocessor every 7 to 125 microseconds and have it jump to a routine which would execute enough contiguous instructions to accomplish the memory refresh, according to externally applied address signals A.sub.0 -A.sub.n or internally applied address signals Q.sub.0 -Q.sub.n generated by a refresh counter internal to the refresh circuit. This is classified as a distribution operation. The timing sequence of the refresh circuit is the period of time between the initiation of a refresh cycle and the initiation of the next refresh cycle.
The refresh timing sequence for a DRAM is regulated by a DRAM controller in response to RAS and CAS signals applied thereto through a clock generator. The DRAM controller and clock generator are external to the individual DRAMs in the bank. Where there are other devices on the line with the memory system in which said devices may interrupt the normal processing operation, or where there is a power down of the memory system, it is necessary that the DRAM device be refreshed during the power down. Where a peripheral device has access to the DRAM memory at the same time that an intentional refresh operation is required to occur, the DRAM controller circuitry will interrupt the memory access to allow the refresh operation to occur. Such an interruption degrades the potential system throughput by as much a ten percent. In a more recent design the DRAM controller circuitry and refresh clock have been incorporated internally on each individual DRAM, regulating the refresh cycle pertinent to the particular DRAM upon which it is fabricated. This eliminates the need for an external DRAM controller and/or clock since each DRAM has its own DRAM controller and refresh clock. This configuration is referred to as a self-refreshing DRAM. Since self-refreshing DRAMs encompass pseudo SRAMs, the more inclusive term, self-refreshing DRAMs, will be used to refer to both self-refreshing DRAMs and pseudo SRAMs. The self-refreshing interruptable DRAM utilizes the same DRAM controller and refresh clock configuration as the self-refreshing DRAM. In some applications both an external clock and controller and an internal clock and controller are employed.
Since the memory system is powered down during refresh, a problem arises with the implementation of internal DRAM controllers and refresh clocks. Since the normal operation of the entire memory must be shut down during the refresh of each self-refreshing interruptable DRAM and since the individual refresh cycles are not synchronized, each self-refreshing interruptable DRAM in the system can potentially shut down the normal operation for an additional period of time equal to the time of the refresh cycle. Each nonsynchronous refresh cycle causes additional wait states. For example, if there are 20 self-refreshing interruptable DRAMs in a bank, the normal processor operation may be shut down a maximum of 20 times for a given refresh cycle if each self-refreshing interruptable DRAM refreshes at a different time than the others. Thus, using self-refreshing interruptable DRAMs can negatively affect the processing speed of the processor.
Additionally, the power requirements are greater with a plurality of self-refreshing DRAMs and self-refreshing interruptable DRAMs and their inherent plurality of DRAM controllers and clock refresh generators. Even in a nondistributed refresh operation, significant power is dissipated in the DRAM controller chip and its associated high-speed system clock driver circuitry.